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A CMOS Low Dropout Regulator with Extended Stable Region for the Effective Series Resistance of the Output CapacitorPAN, Hsuan-I; CHEN, Chern-Lin.IEICE transactions on electronics. 2008, Vol 91, Num 8, pp 1356-1364, issn 0916-8524, 9 p.Article

Low voltage high performance CCII for analog signal processing applicationsRAJPUT, S. S; JAMUAR, S. S.Microelectronics international. 2006, Vol 23, Num 1, pp 10-15, issn 1356-5362, 6 p.Article

Device mismatch and tradeoffs in the design of analog circuitsKINGET, Peter R.IEEE journal of solid-state circuits. 2005, Vol 40, Num 6, pp 1212-1224, issn 0018-9200, 13 p.Article

Chaos engineering and its application to parallel distributed processing with chaotic neural networksAIHARA, Kazuyuki.Proceedings of the IEEE. 2002, Vol 90, Num 5, pp 919-930, issn 0018-9219Article

Electrical characterization of analogue and RF integrated circuits by thermal measurementsMATEO, D; ALTET, J; ALDRETE-VIDRIO, E et al.Microelectronics journal. 2007, Vol 38, Num 2, pp 151-156, issn 0959-8324, 6 p.Conference Paper

A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designsLIHONG ZHANG; RAUT, Rabin; YINGTAO JIANG et al.International journal of circuit theory and applications. 2005, Vol 33, Num 6, pp 487-501, issn 0098-9886, 15 p.Article

Geometrically-constrained, parasitic-aware synthesis of analog ICsCASTRO-LOPEZ, Rafael; FERNANDEZ, Francisco V; RODRIGUEZ VAZQUEZ, Angel et al.Proceedings of SPIE - the International Society for Optical Engineering. 2005, isbn 0-8194-5832-5, 2Vol, vol2, 673-684Conference Paper

Designing SRCOs by combining SPICE and Verilog-ATLELO-CUAUTLE, E; DUARTE-VILLASENOR, M.-A; GARCIA-ORTEGA, J.-M et al.International journal of electronics. 2007, Vol 94, Num 3-4, pp 373-379, issn 0020-7217, 7 p.Article

A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-ampsRAMIREZ-ANGULO, Jaime; SAWANT, Milind; LOPEZ-MARTIN, Antonio et al.Integration (Amsterdam). 2008, Vol 41, Num 4, pp 539-543, issn 0167-9260, 5 p.Article

An Externally Trimmed Integrated DC Current Regulator Insensitive to Conducted EMIREDOUTE, Jean-Michel; WALRAVENS, Cedric; VAN WINCKEL, Steven et al.IEEE transactions on electromagnetic compatibility. 2008, Vol 50, Num 1, pp 63-70, issn 0018-9375, 8 p.Article

A complementary switched MOSFET architecture for the 1/f noise reduction in linear analog CMOS ICsKOH, Jeongwook; SCHMITT-LANDSIEDEL, Doris; THEWES, Roland et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 6, pp 1352-1361, issn 0018-9200, 10 p.Article

A CMOS chopper offset-stabilized opampWITTE, Johan F; MAKINWA, Kofi A. A; HUIJSING, Johan H et al.IEEE journal of solid-state circuits. 2007, Vol 42, Num 7, pp 1529-1535, issn 0018-9200, 7 p.Conference Paper

Bum-in stress test of analog CMOS ICsWEY, Chin-Long; LIU, Meng-Yao.Asian test symposium. 2004, pp 360-365, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

A circuit design based approach for 1/f-noise reduction in linear analog CMOS IC'sKOH, Jeongwook; THEWES, Roland; SCHMITT-LANDSIEDEL, Doris et al.Symposium on VLSI Circuits. 2003, pp 222-225, isbn 0-7803-8287-0, 1Vol, 4 p.Conference Paper

Integrated chaos generatorsDELGADO-RESTITUTO, Manuel; RODRIGUEZ-VAZQUEZ, Angel.Proceedings of the IEEE. 2002, Vol 90, Num 5, pp 747-767, issn 0018-9219Article

Noise considerations in low voltage CMOS integrated temperature sensorsFERRI, G; D'AMICO, A; DI NATALE, C et al.Sensors and actuators. A, Physical. 2000, Vol 85, Num 1-3, pp 232-238, issn 0924-4247Conference Paper

International mixed-signals testing workshopKAMINSKA, Bozena; SUNTER, Stephen; MIR, Salvador et al.Microelectronics journal. 2005, Vol 36, Num 12, issn 0959-8324, 62 p.Conference Proceedings

Design of multiple-metal stacked inductors incorporating an extended physical modelMURPHY, Olive H; MCCARTHY, Kevin G; DELABIE, Christophe J. P et al.IEEE transactions on microwave theory and techniques. 2005, Vol 53, Num 6, pp 2063-2072, issn 0018-9480, 10 p., 2Conference Paper

A simple noise modeling based testing of CMOS analog integrated circuitsYELLAMPALLI, Siva; SRIVASTAVA, Ashok.Proceedings of SPIE, the International Society for Optical Engineering. 2005, pp 276-283, issn 0277-786X, isbn 0-8194-5839-2, 1Vol, 8 p.Conference Paper

A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOSZHIHENG CAO; SHOULI YAN; YUNCHU LI et al.IEEE journal of solid-state circuits. 2009, Vol 44, Num 3, pp 862-873, issn 0018-9200, 12 p.Article

Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond : High-speed I/O channelsMIKE PENG LI.IEEE transactions on advanced packaging. 2009, Vol 32, Num 2, pp 290-297, issn 1521-3323, 8 p.Article

Frequency multiplier using pulse-width control loopSANJAY KUMAR WADHWA.International journal of electronics. 2010, Vol 97, Num 3-4, pp 415-420, issn 0020-7217, 6 p.Article

Realization of log-domain high-order transfer functions using first-order building blocks and complementary operatorsPSYCHALINOS, Costas.International journal of circuit theory and applications. 2007, Vol 35, Num 1, pp 17-32, issn 0098-9886, 16 p.Article

Lumped-element analysis and design of CMOS distributed amplifiers with image impedance terminationMOEZ, Kambiz K; ELMASRY, Mohamed I.Microelectronics journal. 2006, Vol 37, Num 10, pp 1136-1145, issn 0959-8324, 10 p.Article

A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory ErrorsCHI HO LAW; HURST, Paul J; LEWIS, Stephen H et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 10, pp 2091-2103, issn 0018-9200, 13 p.Article

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